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» Practical techniques to reduce skew and its variations in bu...
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DAC
2009
ACM
14 years 1 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
ISPD
2010
ACM
177views Hardware» more  ISPD 2010»
14 years 1 months ago
Skew management of NBTI impacted gated clock trees
NBTI (Negative Bias Temperature Instability) has emerged as the dominant failure mechanism for PMOS in nanometer IC designs. However, its impact on one of the most important compo...
Ashutosh Chakraborty, David Z. Pan
DAC
1997
ACM
13 years 10 months ago
More Practical Bounded-Skew Clock Routing
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...
Andrew B. Kahng, Chung-Wen Albert Tsao
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
14 years 3 months ago
Combinatorial algorithms for fast clock mesh optimization
We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the hi...
Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li
CCS
2006
ACM
13 years 10 months ago
Hot or not: revealing hidden services by their clock skew
Location-hidden services, as offered by anonymity systems such as Tor, allow servers to be operated under a pseudonym. As Tor is an overlay network, servers hosting hidden service...
Steven J. Murdoch