287 search results - page 45 / 58 » Predicate-Aware Scheduling: A Technique for Reducing Resourc... |
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
This paper proposes a novel Behavioral Synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional...
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ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...
RTAS
2008
IEEE
15 years 4 months ago
2008
IEEE
Many wireless sensor nodes (motes) interface with slow peripheral devices, requiring the processor to wait. These delays waste time, energy and power, which are valuable but limit...
ISLPED
2009
ACM
15 years 4 months ago
2009
ACM
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
- The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...