Sciweavers

287 search results - page 49 / 58
» Predicate-Aware Scheduling: A Technique for Reducing Resourc...
Sort
View
FPL
2003
Springer
95views Hardware» more  FPL 2003»
15 years 2 months ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
MOBISYS
2004
ACM
15 years 9 months ago
NWSLite: A Light-Weight Prediction Utility for Mobile Devices
Computation off-loading, i.e., remote execution, has been shown to be effective for extending the computational power and battery life of resource-restricted devices, e.g., hand-h...
Selim Gurun, Chandra Krintz, Richard Wolski
ICDE
2007
IEEE
134views Database» more  ICDE 2007»
15 years 4 months ago
Outlier Detection for Fine-grained Load Balancing in Database Clusters
Recent industry trends towards reducing the costs of ownership in large data centers emphasize the need for database system techniques for both automatic performance tuning and ef...
Jin Chen, Gokul Soundararajan, Madalin Mihailescu,...
FPGA
2004
ACM
128views FPGA» more  FPGA 2004»
15 years 1 months ago
Incremental physical resynthesis for timing optimization
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...
CODES
2010
IEEE
14 years 6 months ago
Hardware/software optimization of error detection implementation for real-time embedded systems
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
Adrian Lifa, Petru Eles, Zebo Peng, Viacheslav Izo...