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LCTRTS
1998
Springer
15 years 1 months ago
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
Thomas Lundqvist, Per Stenström
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
14 years 9 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
BMCBI
2011
14 years 1 months ago
LAVA: An Open-Source Approach To Designing LAMP (Loop-Mediated Isothermal Amplification) DNA Signatures
Background: We developed an extendable open-source Loop-mediated isothermal AMPlification (LAMP) signature design program called LAVA (LAMP Assay Versatile Analysis). LAVA was cre...
Clinton Torres, Elizabeth A. Vitalis, Brian R. Bak...
MAM
2006
124views more  MAM 2006»
14 years 9 months ago
Design optimization and space minimization considering timing and code size via retiming and unfolding
The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such a...
Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, M...
SOFSEM
2010
Springer
15 years 6 months ago
Practically Applicable Formal Methods
Abstract. Formal methods are considered to be highly expensive. Therefore, they are currently applied almost only in high risk software development. In this paper, we show that for...
Jedrzej Fulara, Krzysztof Jakubczyk