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» Predictable Instruction Caching for Media Processors
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IEEEPACT
2000
IEEE
15 years 4 months ago
The Effect of Code Reordering on Branch Prediction
Branch prediction accuracy is a very important factor for superscalarprocessor performance. The ability topredict the outcome of a branch allows the processor to effectively use a...
Alex Ramírez, Josep-Lluis Larriba-Pey, Mate...
100
Voted
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
15 years 4 months ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi
SPAA
2006
ACM
15 years 5 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
103
Voted
ACMSE
2004
ACM
15 years 5 months ago
Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite
Replacement policy, one of the key factors determining the effectiveness of a cache, becomes even more important with latest technological trends toward highly associative caches....
Hussein Al-Zoubi, Aleksandar Milenkovic, Milena Mi...
CCS
2007
ACM
15 years 5 months ago
Yet another MicroArchitectural Attack: : exploiting I-Cache
Abstract. MicroArchitectural Attacks (MA), which can be considered as a special form of SideChannel Analysis, exploit microarchitectural functionalities of processor implementation...
Onur Aciiçmez