86 search results - page 16 / 18 » Predictable Instruction Caching for Media Processors |
100
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ISCA
2007
IEEE
15 years 6 months ago
2007
IEEE
The negative performance impact of branch mis-predictions can be reduced by exploiting control independence (CI). When a branch mis-predicts, the wrong-path instructions up to the...
HPCA
2001
IEEE
16 years 9 hour ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
100
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ASAP
2007
IEEE
15 years 3 months ago
2007
IEEE
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...
MICRO
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
141
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CODES
2004
IEEE
15 years 3 months ago
2004
IEEE
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...