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» Predictable Paging in Real-Time Systems: A Compiler Approach
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JIRS
2008
100views more  JIRS 2008»
14 years 9 months ago
Model-based Predictive Control of Hybrid Systems: A Probabilistic Neural-network Approach to Real-time Control
Abstract This paper proposes an approach for reducing the computational complexity of a model-predictive-control strategy for discrete-time hybrid systems with discrete inputs only...
Bostjan Potocnik, Gasper Music, Igor Skrjanc, Boru...
79
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CASES
2008
ACM
14 years 11 months ago
Exploring and predicting the architecture/optimising compiler co-design space
Embedded processor performance is dependent on both the underlying architecture and the compiler optimisations applied. However, designing both simultaneously is extremely difficu...
Christophe Dubach, Timothy M. Jones, Michael F. P....
ICS
1999
Tsinghua U.
15 years 1 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer
ASPDAC
2004
ACM
107views Hardware» more  ASPDAC 2004»
15 years 2 months ago
Fast, predictable and low energy memory references through architecture-aware compilation
The design of future high-performance embedded systems is hampered by two problems: First, the required hardware needs more energy than is available from batteries. Second, curren...
Peter Marwedel, Lars Wehmeyer, Manish Verma, Stefa...
RTCSA
2009
IEEE
15 years 4 months ago
Branch Target Buffers: WCET Analysis Framework and Timing Predictability
—One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis h...
Daniel Grund, Jan Reineke, Gernot Gebhard