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HICSS
2009
IEEE
107views Biometrics» more  HICSS 2009»
15 years 8 months ago
EM Enforcing Information Flow Properties using Compensating Events
Deeply embedded infrastructures are pervasive systems that have significant cyber and physical components, interacting with each other in complex ways. These interactions can vio...
Thoshitha T. Gamage, Bruce M. McMillin
SBRN
2000
IEEE
15 years 6 months ago
Non-Linear Modelling and Chaotic Neural Networks
This paper proposes a simple methodology to construct an iterative neural network which mimics a given chaotic time series. The methodology uses the Gamma test to identify a suita...
Antonia J. Jones, Steve Margetts, Peter Durrant, A...
IESS
2007
Springer
120views Hardware» more  IESS 2007»
15 years 8 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
USENIX
2003
15 years 3 months ago
Design and Implementation of Power-Aware Virtual Memory
Despite constant improvements in fabrication technology, hardware components are consuming more power than ever. With the everincreasing demand for higher performance in highly-in...
Hai Huang, Padmanabhan Pillai, Kang G. Shin
ICCAD
2004
IEEE
118views Hardware» more  ICCAD 2004»
15 years 10 months ago
Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization
New embedded systems offer rich power management features in the form of multiple operational and non-operational power modes. While they offer mechanisms for better energy effic...
Jinfeng Liu, Pai H. Chou