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2004
Tsinghua U.
15 years 10 months ago
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
Rajeev Balasubramonian
MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
15 years 9 months ago
A Dynamic Multithreading Processor
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
Haitham Akkary, Michael A. Driscoll
FASE
2010
Springer
15 years 11 months ago
Evaluating Ordering Heuristics for Dynamic Partial-Order Reduction Techniques
Actor programs consist of a number of concurrent objects called actors, which communicate by exchanging messages. Nondeterminism in actors results from the different possible orde...
Steven Lauterburg, Rajesh K. Karmani, Darko Marino...
EDBT
2009
ACM
148views Database» more  EDBT 2009»
15 years 8 months ago
MVT: a schema mapping validation tool
Schema mappings define relationships between schemas in a declarative way. We demonstrate MVT, a mapping validation tool that allows the designer to ask whether the mapping has ce...
Guillem Rull, Carles Farré, Ernest Teniente...
DSD
2005
IEEE
96views Hardware» more  DSD 2005»
15 years 6 months ago
Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
Peter Filter, Hana Kubatova