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HPCA
2003
IEEE
15 years 10 months ago
Active I/O Switches in System Area Networks
We present an active switch architecture to improve the performance of systems connected via system area networks. Our programmable active switches not only flexibly route packets...
Ming Hao, Mark Heinrich
SC
2009
ACM
15 years 4 months ago
Enabling high-fidelity neutron transport simulations on petascale architectures
The UNIC code is being developed as part of the DOE’s Nuclear Energy Advanced Modeling and Simulation (NEAMS) program. UNIC is an unstructured, deterministic neutron transport c...
Dinesh K. Kaushik, Micheal Smith, Allan Wollaber, ...
PPOPP
2005
ACM
15 years 3 months ago
Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, A...
BMCBI
2006
130views more  BMCBI 2006»
14 years 9 months ago
MicroTar: predicting microRNA targets from RNA duplexes
Background: The accurate prediction of a comprehensive set of messenger RNAs (targets) regulated by animal microRNAs (miRNAs) remains an open problem. In particular, the predictio...
Rahul Thadani, Martti T. Tammi
ASPLOS
2009
ACM
15 years 10 months ago
Phantom-BTB: a virtualized branch target buffer design
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
Ioana Burcea, Andreas Moshovos