Sciweavers

874 search results - page 111 / 175
» Predicting the Running Times of Parallel Programs by Simulat...
Sort
View
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
15 years 1 months ago
Tempest and Typhoon: User-Level Shared Memory
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...
Steven K. Reinhardt, James R. Larus, David A. Wood
DATE
2010
IEEE
178views Hardware» more  DATE 2010»
15 years 2 months ago
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...
FPL
2004
Springer
101views Hardware» more  FPL 2004»
15 years 3 months ago
The Chess Monster Hydra
Abstract. With the help of the FPGA technology, the boarder between hardand software has vanished. It is now possible to develop complex designs and fine grained parallel applicat...
Chrilly Donninger, Ulf Lorenz
SOSP
1989
ACM
14 years 11 months ago
Process Control and Scheduling Issues for Multiprogrammed Shared-Memory Multiprocessors
Shared-memory multiprocessors are frequently used in a timesharing style with multiple parallel applications executing at the same time. In such an environment, where the machine ...
Andrew Tucker, Anoop Gupta
BCS
2008
14 years 11 months ago
A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming
This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. ...
Andreas Fidjeland, Wayne Luk, Stephen Muggleton