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CLUSTER
2004
IEEE
15 years 1 months ago
FTC-Charm++: an in-memory checkpoint-based fault tolerant runtime for Charm++ and MPI
As high performance clusters continue to grow in size, the mean time between failure shrinks. Thus, the issues of fault tolerance and reliability are becoming one of the challengi...
Gengbin Zheng, Lixia Shi, Laxmikant V. Kalé
89
Voted
SPAA
2006
ACM
15 years 3 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
HPCA
2012
IEEE
13 years 5 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
ICS
2007
Tsinghua U.
15 years 3 months ago
Performance driven data cache prefetching in a dynamic software optimization system
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
Jean Christophe Beyler, Philippe Clauss
ICDCS
2003
IEEE
15 years 2 months ago
Performance Guarantees for Cluster-Based Internet Services
As web-based transactions become an essential element of everyday corporate and commerce activities, it becomes increasingly important that the performance of web-based services b...
Chang Li, Gang Peng, Kartik Gopalan, Tzi-cker Chiu...