7 search results - page 2 / 2 » Prediction of high-performance on-chip global interconnectio... |
ASYNC
2002
IEEE
15 years 2 months ago
2002
IEEE
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
OOPSLA
2005
Springer
15 years 3 months ago
2005
Springer
It is now well established that the device scaling predicted by Moore’s Law is no longer a viable option for increasing the clock frequency of future uniprocessor systems at the...