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MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
15 years 5 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
MICRO
2002
IEEE
143views Hardware» more  MICRO 2002»
15 years 4 months ago
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
Enric Gibert, F. Jesús Sánchez, Anto...
CVPR
2003
IEEE
16 years 1 months ago
Multi-modal image registration by minimizing Kullback-Leibler distance between expected and observed joint class histograms
In this paper, we present a new multimodal image registration method based on the a priori knowledge of the class label mappings between two segmented input images. A joint class ...
Ho-Ming Chan, Albert C. S. Chung, Simon C. H. Yu, ...
DAC
2004
ACM
16 years 11 days ago
Memory access scheduling and binding considering energy minimization in multi-bank memory systems
Memory-related activity is one of the major sources of energy consumption in embedded systems. Many types of memories used in embedded systems allow multiple operating modes (e.g....
Chun-Gi Lyuh, Taewhan Kim
SAS
2007
Springer
108views Formal Methods» more  SAS 2007»
15 years 5 months ago
Programming Language Design and Analysis Motivated by Hardware Evolution
Abstract. Silicon chip design has passed a threshold whereby exponentially increasing transistor density (Moore’s Law) no longer translates into increased processing power for si...
Alan Mycroft