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IEEEPACT
2005
IEEE
15 years 9 months ago
Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
Yonghong Song, Spiros Kalogeropulos, Partha Tiruma...
WORDS
2005
IEEE
15 years 9 months ago
A Framework for Simplifying the Development of Kernel Schedulers: Design and Performance Evaluation
Writing a new scheduler and integrating it into an existing OS is a daunting task, requiring the understanding of multiple low-level kernel mechanisms. Indeed, implementing a new ...
Gilles Muller, Julia L. Lawall, Hervé Duche...
126
Voted
ANCS
2005
ACM
15 years 9 months ago
High-throughput linked-pattern matching for intrusion detection systems
This paper presents a hardware architecture for highly efficient intrusion detection systems. In addition, a software tool for automatically generating the hardware is presented....
Zachary K. Baker, Viktor K. Prasanna
190
Voted
ANCS
2005
ACM
15 years 9 months ago
Gigabit routing on a software-exposed tiled-microprocessor
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...
Umar Saif, James W. Anderson, Anthony Degangi, Ana...
FPL
2005
Springer
98views Hardware» more  FPL 2005»
15 years 9 months ago
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs
Modern heterogeneous FPGAs contain “hard” specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible “soft” programmable ...
Peter Jamieson, Jonathan Rose