Sciweavers

3796 search results - page 51 / 760
» Presentations by Programmers for Programmers
Sort
View
FPL
2008
Springer
96views Hardware» more  FPL 2008»
14 years 11 months ago
Low-latency high-bandwidth HW/SW communication in a virtual memory environment
Adaptive computers combine conventional software programmable processors with reconfigurable compute units. We present techniques that allow the high-performance realization of de...
Holger Lange, Andreas Koch
ERSA
2006
105views Hardware» more  ERSA 2006»
14 years 11 months ago
A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture
In a coarse-grained reconfigurable architecture, the functions of resources such as Arithmetic Logic Units (ALUs) can be reconfigured. Unlike the programmability of a general purp...
Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit
103
Voted
ESANN
2006
14 years 11 months ago
Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic
Abstract. Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choic...
Benjamin Schrauwen, Jan M. Van Campenhout
COOTS
1998
14 years 11 months ago
Execution Patterns in Object-Oriented Visualization
Execution patterns are a new metaphor for visualizing execution traces of object-oriented programs. We present an execution pattern view that lets a programmer visualize and explo...
Wim De Pauw, David H. Lorenz, John M. Vlissides, M...
FPL
2010
Springer
210views Hardware» more  FPL 2010»
14 years 7 months ago
A Compact Transactional Memory Multiprocessor System on FPGA
In this paper we present a rapid prototyping platform on a single Field Programmable Gate Array (FPGA) with support for software transactional memory. The system is composed only b...
Matteo Pusceddu, Simone Ceccolini, Gianluca Palerm...