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127
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ISCAS
2008
IEEE
15 years 11 months ago
2008
IEEE
Abstract— We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tailbiting LDPC convolutional codes. This archite...
108
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper presents the design and study of reconfigurable architectures for two data-link layer frame delineation techniques used for ATM and GFP. The architectures are targeted ...
136
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APN
2001
Springer
15 years 8 months ago
2001
Springer
We address the verification of programmable logic controllers (PLC). In our approach, a PLC program is translated into a special type of colored Petri net, a so-called register net...
122
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IJCAI
1989
15 years 5 months ago
1989
A cognitive model of student programmers is presented. The model is based on protocol studies of students writing Pascal programs, and is implemented in a computer simulation prog...
149
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VLSID
2006
IEEE
15 years 10 months ago
2006
IEEE
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...