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» Presentations of Structures in Admissible Sets
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81
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VTS
1997
IEEE
86views Hardware» more  VTS 1997»
15 years 5 months ago
Incremental logic rectification
We address the problem of rectifying an incorrect combinational circuit against a given specification. Based on the symbolic BDD techniques, we consider the rectification process,...
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
131
Voted
ISMIS
1997
Springer
15 years 5 months ago
Knowledge-Based Image Retrieval with Spatial and Temporal Constructs
e about image features can be expressed as a hierarchical structure called a Type Abstraction Hierarchy (TAH). TAHs can be generated automatically by clustering algorithms based on...
Wesley W. Chu, Alfonso F. Cardenas, Ricky K. Taira
VR
1993
IEEE
15 years 5 months ago
A Virtual World for Network Management
Existing network management systems typically use a combination of textual displays and 2D directed graph representations of network topology. We are designing a network managemen...
Steven Feiner, Michelle X. Zhou, Laurence A. Crutc...
WG
1993
Springer
15 years 4 months ago
Graphs, Hypergraphs and Hashing
Minimal perfect hash functions are used for memory efficient storage and fast retrieval of items from static sets. We present an infinite family of efficient and practical algori...
George Havas, Bohdan S. Majewski, Nicholas C. Worm...
86
Voted
ASPDAC
2007
ACM
133views Hardware» more  ASPDAC 2007»
15 years 4 months ago
Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM
- For sub-90nm technology nodes and below, random fluctuations of within-die physical process properties are also known as random on-chip variation (OCV). It impacts on the VLSI/So...
Jun-Fu Huang, Victor C. Y. Chang, Sally Liu, Kelvi...