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ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
15 years 5 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
160
Voted
JNW
2008
354views more  JNW 2008»
15 years 5 months ago
On the 20/40 MHz Coexistence of Overlapping BSSs in WLANs
Abstract-- We investigate the impact of 20/40 MHz coexistence on the performance of wireless local area networks (WLANs). To that end, we present simulation results of overlapping ...
Ariton E. Xhafa, Anuj Batra, Artur Zaks
VLSISP
2008
173views more  VLSISP 2008»
15 years 4 months ago
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence...
Yedidya Hilewitz, Ruby B. Lee
CCR
2004
95views more  CCR 2004»
15 years 4 months ago
A Per-Domain Behavior for circuit emulation in IP networks
Circuit networks are expensive to build, difficult to operate, fragile, and not easily scalable. Many network operators would like to carry circuit traffic as an overlay on top of...
Kathleen M. Nichols, Van Jacobson, Kedarnath Podur...
JIRS
2000
144views more  JIRS 2000»
15 years 4 months ago
An Integrated Approach of Learning, Planning, and Execution
Agents (hardware or software) that act autonomously in an environment have to be able to integrate three basic behaviors: planning, execution, and learning. This integration is man...
Ramón García-Martínez, Daniel...