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ICPP
2008
IEEE
15 years 11 months ago
Implementing and Exploiting Inevitability in Software Transactional Memory
—Transactional Memory (TM) takes responsibility for concurrent, atomic execution of labeled regions of code, freeing the programmer from the need to manage locks. Typical impleme...
Michael F. Spear, Michael Silverman, Luke Dalessan...
IISWC
2008
IEEE
15 years 11 months ago
A workload for evaluating deep packet inspection architectures
—High-speed content inspection of network traffic is an important new application area for programmable networking systems, and has recently led to several proposals for high-per...
Michela Becchi, Mark A. Franklin, Patrick Crowley
INFOCOM
2008
IEEE
15 years 11 months ago
Association Control in Mobile Wireless Networks
—As mobile nodes roam in a wireless network, they continuously associate with different access points and perform handoff operations. However, these handoffs can potentially incu...
Minkyong Kim, Zhen Liu, Srinivasan Parthasarathy 0...
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IPPS
2008
IEEE
15 years 11 months ago
DC-SIMD : Dynamic communication for SIMD processors
SIMD (single instruction multiple data)-type processors have been found very efficient in image processing applications, because their repetitive structure is able to exploit the...
Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Co...
MICRO
2008
IEEE
111views Hardware» more  MICRO 2008»
15 years 11 months ago
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...
Livio Soares, David K. Tam, Michael Stumm