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FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
15 years 3 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
15 years 3 months ago
VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks
Recent technological advances have produced network interfaces that provide users with very low-latency access to the memory of remote machines. We examine the impact of such netw...
Leonidas I. Kontothanassis, Galen C. Hunt, Robert ...
HPDC
1996
IEEE
15 years 3 months ago
Legion - A View from 50, 000 Feet
' The coming of giga-bit networks makes possible the realization ofa single nationwide virtual computer comprised of a variety of geographically distributed highpe6ormance mac...
Andrew S. Grimshaw, William A. Wulf
CASES
2007
ACM
15 years 3 months ago
A simplified java bytecode compilation system for resource-constrained embedded processors
Embedded platforms are resource-constrained systems in which performance and memory requirements of executed code are of critical importance. However, standard techniques such as ...
Carmen Badea, Alexandru Nicolau, Alexander V. Veid...
CASES
2007
ACM
15 years 3 months ago
Scratch-pad memory allocation without compiler support for java applications
ABSTRACT This paper presents the first scratch-pad memory allocation scheme that requires no compiler support for interpreted-language based applications. A scratch-pad memory (SPM...
Nghi Nguyen, Angel Dominguez, Rajeev Barua