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ISSS
1997
IEEE
109views Hardware» more  ISSS 1997»
15 years 7 months ago
Reducing the Complexity of ILP Formulations for Synthesis
Integer Linear Programming ILP is commonly used in high level and system level synthesis. It is an NP-Complete problem in general cases. There exists some tools that give an o...
Anne Mignotte, Olivier Peyran
RTSS
1996
IEEE
15 years 7 months ago
A framework for implementing objects and scheduling tasks in lock-free real-time systems
We present an integrated framework for developing realtime systems in which lock-free algorithms are employed to implement shared objects. There are two key objectives of our work...
James H. Anderson, Srikanth Ramamurthy
EURODAC
1994
IEEE
186views VHDL» more  EURODAC 1994»
15 years 7 months ago
Algorithms for a switch module routing problem
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
Shashidhar Thakur, D. F. Wong, S. Muthukrishnan
ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
15 years 7 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
ISCAS
1994
IEEE
104views Hardware» more  ISCAS 1994»
15 years 7 months ago
A Graph-Theoretic Approach to Clock Skew Optimization
This paper addresses the problem of minimizing the clock period of a circuit by optimizingthe clock skews. We incorporate uncertainty factors and present a formulation that ensure...
Rahul B. Deokar, Sachin S. Sapatnekar