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158
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DATE
2000
IEEE
15 years 9 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
159
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ICPP
1999
IEEE
15 years 9 months ago
1999
IEEE
There has been much work recently on improving the locality performance of loop nests in scientific programs through the use of loop as well as data layout optimizations. However,...
116
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ASPDAC
2008
ACM
15 years 6 months ago
2008
ACM
In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits. The number of constraints and variables ...
152
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CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, trad...
135
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IJRR
2008
15 years 4 months ago
2008
This paper deals with minimum time trajectory optimization along a specified path subject to thermal constraints. We point out here that robots are often integrated in complex rob...