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WCRE
2002
IEEE
15 years 9 months ago
Register Liveness Analysis for Optimizing Dynamic Binary Translation
Dynamic binary translators compile machine code from a source architecture to a target architecture at run time. Due to the hard time constraints of just-in-time compilation only ...
Mark Probst, Andreas Krall, Bernhard Scholz
ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
15 years 9 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...
135
Voted
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
15 years 9 months ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen
ICCL
1998
IEEE
15 years 9 months ago
Loop Optimization for Aggregate Array Computations
An aggregate array computation is a loop that computes accumulated quantities over array elements. Such computations are common in programs that use arrays, and the array elements...
Yanhong A. Liu, Scott D. Stoller
DASFAA
1997
IEEE
112views Database» more  DASFAA 1997»
15 years 9 months ago
Client-Server Optimization for Multimedia Document Exchange
The success of the World Wide Web is boosting the development of multimedia database systems and their integration into the internet. For the documents stored and exchanged in the...
Gerhard Köstler, Wolfgang L. J. Kowarschick, ...