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VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
15 years 8 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
ICRA
1998
IEEE
142views Robotics» more  ICRA 1998»
15 years 8 months ago
Lagrangian Relaxation Neural Networks for Job Shop Scheduling
Abstract--Manufacturing scheduling is an important but difficult task. In order to effectively solve such combinatorial optimization problems, this paper presents a novel Lagrangia...
Peter B. Luh, Xing Zhao, Yajun Wang
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
15 years 8 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
ICCAD
1994
IEEE
114views Hardware» more  ICCAD 1994»
15 years 8 months ago
Performance-driven synthesis of asynchronous controllers
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...
Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas ...
GECCO
2006
Springer
168views Optimization» more  GECCO 2006»
15 years 8 months ago
3D airspace sectoring by evolutionary computation: real-world applications
This paper presents a new method for 3D cutting of geometrical space with application to airspace sectoring. This problem comes from the air traffic management but the proposed me...
Daniel Delahaye, Stephane Puechmorel