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IEEEPACT
2005
IEEE
15 years 6 months ago
HUNTing the Overlap
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
Costin Iancu, Parry Husbands, Paul Hargrove
118
Voted
ICS
2004
Tsinghua U.
15 years 6 months ago
CQoS: a framework for enabling QoS in shared caches of CMP platforms
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
Ravi R. Iyer
HPDC
2012
IEEE
13 years 3 months ago
vSlicer: latency-aware virtual machine scheduling via differentiated-frequency CPU slicing
Recent advances in virtualization technologies have made it feasible to host multiple virtual machines (VMs) in the same physical host and even the same CPU core, with fair share ...
Cong Xu, Sahan Gamage, Pawan N. Rao, Ardalan Kanga...
ICPADS
2006
IEEE
15 years 6 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
EDBT
2009
ACM
112views Database» more  EDBT 2009»
15 years 5 months ago
GCIP: exploiting the generation and optimization of integration processes
As a result of the changing scope of data management towards the management of highly distributed systems and applications, integration processes have gained in imporuch integrati...
Matthias Böhm, Uwe Wloka, Dirk Habich, Wolfga...