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CODES
2003
IEEE
15 years 11 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
ISCAS
2003
IEEE
131views Hardware» more  ISCAS 2003»
15 years 11 months ago
Process variation dimension reduction based on SVD
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...
Zhuo Li, Xiang Lu, Weiping Shi
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
15 years 11 months ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
ASAP
2002
IEEE
105views Hardware» more  ASAP 2002»
15 years 11 months ago
Implications of Programmable General Purpose Processors for Compression/Encryption Applications
With the growth of the Internet and mobile communication industry, multimedia applications form a dominant computer workload. Media workloads are typically executed on Application...
Byeong Kil Lee, Lizy Kurian John
WCRE
1999
IEEE
15 years 10 months ago
Experiments with Clustering as a Software Remodularization Method
As valuable software systems get old, reverse engineering becomes more and more important to the companies that have to maintain the code. Clustering is a key activity in reverse ...
Nicolas Anquetil, Timothy Lethbridge
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