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» Problem Structure and Dependable Architecture
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79
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ICCD
2006
IEEE
104views Hardware» more  ICCD 2006»
15 years 9 months ago
Guiding Architectural SRAM Models
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
Banit Agrawal, Timothy Sherwood
CASES
2007
ACM
15 years 4 months ago
Towards understanding architectural tradeoffs in MEMS closed-loop feedback control
Micro-Electro-Mechanical Systems (MEMS) combine lithographically formed mechanical structures with electrical elements to create physical systems that operate on the scale of micr...
Greg Hoover, Forrest Brewer, Timothy Sherwood
SIGMETRICS
2008
ACM
181views Hardware» more  SIGMETRICS 2008»
15 years 15 days ago
Counter braids: a novel counter architecture for per-flow measurement
Fine-grained network measurement requires routers and switches to update large arrays of counters at very high link speed (e.g. 40 Gbps). A naive algorithm needs an infeasible amo...
Yi Lu, Andrea Montanari, Balaji Prabhakar, Sarang ...
81
Voted
LREC
2008
113views Education» more  LREC 2008»
15 years 2 months ago
Treebank-Based Acquisition of LFG Parsing Resources for French
Motivated by the expense in time and other resources to produce hand-crafted grammars, there has been increased interest in automatically obtained wide-coverage grammars from tree...
Natalie Schluter, Josef van Genabith
80
Voted
DFT
2007
IEEE
86views VLSI» more  DFT 2007»
15 years 7 months ago
Production Yield and Self-Configuration in the Future Massively Defective Nanochips
We address two problems in this work, namely, 1) the resilience challenge in the future chips made up of massively defective nanoelements and organized in replicative multicore ar...
Piotr Zajac, Jacques Henri Collet