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FPGA
2000
ACM
177views FPGA» more  FPGA 2000»
15 years 7 months ago
Automatic generation of FPGA routing architectures from high-level descriptions
In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. W...
Vaughn Betz, Jonathan Rose
DLOG
2006
15 years 5 months ago
Tableau Caching for Description Logics with Inverse and Transitive Roles
Abstract. Modern description logic (DL) reasoners are known to be less efficient for DLs with inverse roles. The current loss of performance is largely due to the missing applicabi...
Yu Ding, Volker Haarslev
JAPLL
2010
141views more  JAPLL 2010»
15 years 2 months ago
Algebraic tableau reasoning for the description logic SHOQ
Semantic web applications based on the web ontology language (OWL) often require the use of numbers in class descriptions for expressing cardinality restrictions on properties or ...
Jocelyne Faddoul, Volker Haarslev
DLOG
2009
15 years 2 months ago
Testing Provers on a Grid - Framework Description
Abstract. GridTest is a framework for testing automated theorem provers using randomly generated formulas. It can be used to run tests locally, in a single computer, or in a comput...
Carlos Areces, Daniel Gorín, Alejandra Lore...
TCAD
2002
135views more  TCAD 2002»
15 years 3 months ago
Area fill synthesis for uniform layout density
Chemical-mechanical polishing (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on local character...
Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexande...