735 search results - page 131 / 147 » Procedural Modeling of Interconnected Structures |
124
click to vote
VLSID
2003
IEEE
16 years 2 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
124
Voted
ICCAD
2006
IEEE
15 years 10 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
INFOCOM
2009
IEEE
15 years 8 months ago
2009
IEEE
Abstract— Although direct reciprocity (Tit-for-Tat) contribution systems have been successful in reducing freeloading in peerto-peer overlays, it has been shown that, unless the ...
DATE
2008
IEEE
15 years 8 months ago
2008
IEEE
— In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly highe...
110
click to vote
ISBI
2007
IEEE
15 years 8 months ago
2007
IEEE
In this paper we present a novel tag removal method for tagged cardiac MR images. This method is based on a 2D bandstop filtering technique, which selectively attenuates the tag ...