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» Procedural Modeling of Interconnected Structures
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97
Voted
FPGA
2008
ACM
173views FPGA» more  FPGA 2008»
15 years 1 months ago
The amorphous FPGA architecture
This paper describes the Amorphous FPGA, an innovative architecture attempting to optimally allocate logic and routing resource on per-mapping basis. Designed for high performance...
Mingjie Lin
87
Voted
DAC
2002
ACM
16 years 18 days ago
A physical model for the transient response of capacitively loaded distributed rlc interconnects
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....
Raguraman Venkatesan, Jeffrey A. Davis, James D. M...
ISPD
2000
ACM
86views Hardware» more  ISPD 2000»
15 years 4 months ago
Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects
500+ MHz designs using deep-submicron (DSM) copper interconnects require accurate and efficient modeling of cladding-metals’ frequency-dependent impedance [1]. In this paper, fo...
Li-Fu Chang, Keh-Jeng Chang, Robert Mathews
90
Voted
CSDA
2008
68views more  CSDA 2008»
14 years 11 months ago
Modelling the US, UK and Japanese unemployment rates: Fractional integration and structural breaks
In this paper we use a general procedure for fractional integration and structural breaks at unknown points in time, which allows for different orders of integration and determini...
Guglielmo Maria Caporale, Luis A. Gil-Alana
ICCAD
2008
IEEE
147views Hardware» more  ICCAD 2008»
15 years 8 months ago
Overlay aware interconnect and timing variation modeling for double patterning technology
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan