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DAC
2008
ACM
15 years 11 months ago
An 8x8 run-time reconfigurable FPGA embedded in a SoC
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. ...
Sumanta Chaudhuri, Sylvain Guilley, Florent Flamen...
ICMCS
2005
IEEE
143views Multimedia» more  ICMCS 2005»
15 years 3 months ago
Rate-distortion estimation for H.264/AVC coders
In a video coder, the optimal coding mode decision for each coding block could be achieved by exhaustively calculating the Lagrange cost (which includes the coding distortion plus...
Yu-Kuang Tu, Jar-Ferr Yang, Ming-Ting Sun
SIGCOMM
1996
ACM
15 years 2 months ago
Speeding up Protocols for Small Messages
Many techniques have been discovered to improve performance of bulk data transfer protocols which use large messages. This paper describes a technique that improves protocol perfo...
Trevor Blackwell
CORR
2010
Springer
99views Education» more  CORR 2010»
14 years 10 months ago
An Automated Algorithm for Approximation of Temporal Video Data Using Linear B'EZIER Fitting
This paper presents an efficient method for approximation of temporal video data using linear Bezier fitting. For a given sequence of frames, the proposed method estimates the int...
Murtaza Ali Khan
ESSCIRC
2011
93views more  ESSCIRC 2011»
13 years 9 months ago
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 volta
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomu...