6819 search results - page 1177 / 1364 » Process Reuse Architecture |
158
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
122
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ISCA
2006
IEEE
15 years 10 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
139
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ISCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
—Linear amplification with nonlinear components (LINC) technique is a linearization technique for power amplifier designs. By using LINC, the nonlinear power amplifier with high ...
116
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ISCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper introduces a novel low-power digital future, are expected to run at frequencies beyond 10 MHz. In controller for high frequency dc-dc switch-mode power supplies addition...
145
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PDP
2006
IEEE
15 years 10 months ago
2006
IEEE
— The Parallel Resource-Optimal (PRO) computation model was introduced by Gebremedhin et al. [2002] as a framework for the design and analysis of efficient parallel algorithms. ...