Sciweavers

6819 search results - page 208 / 1364
» Process Reuse Architecture
Sort
View
145
Voted
MIRRORBOT
2005
Springer
144views Robotics» more  MIRRORBOT 2005»
15 years 9 months ago
Combining Visual Attention, Object Recognition and Associative Information Processing in a NeuroBotic System
We have implemented a neurobiologically plausible system on a robot that integrates visual attention, object recognition, language and action processing using a coherent cortex-lik...
Rebecca Fay, Ulrich Kaufmann, Andreas Knoblauch, H...
ICCD
1992
IEEE
124views Hardware» more  ICCD 1992»
15 years 8 months ago
The ETCA Data-Flow Functional Computer for Real-Time Image Processing
This paper presents a data- ow computer, constituted of a large array of data- ow processors and programmed using a functional language, and its application to realtime image proc...
Georges Quénot, Bertrand Zavidovique
CORR
2010
Springer
135views Education» more  CORR 2010»
15 years 3 months ago
Gravitational tree-code on graphics processing units: implementation in CUDA
We present a new very fast tree-code which runs on massively parallel Graphical Processing Units (GPU) with NVIDIA CUDA architecture. The tree-construction and calculation of mult...
Evghenii Gaburov, Jeroen Bédorf, Simon Port...
ICSE
2003
IEEE-ACM
15 years 9 months ago
Architectural Requirements Engineering: Theory vs. Practice
This paper discusses how architectural requirements engineering fits into an overall software development process in the concept and definition phases of a project. It defines a r...
Robert W. Schwanke
GLVLSI
2005
IEEE
118views VLSI» more  GLVLSI 2005»
15 years 9 months ago
A continuous time markov decision process based on-chip buffer allocation methodology
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Dob...