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ICIP
2009
IEEE
16 years 5 months ago
Architecture Design Of A High-performance Dual-symbol Binary Arithmetic Coder For Jpeg2000
The embedded-block coding with optimized truncation (EBCOT), which consists of a bit-plane coder (BPC) and a binary arithmetic coder (BAC), is the bottleneck in realizing a high-p...
VLDB
2003
ACM
172views Database» more  VLDB 2003»
16 years 4 months ago
Aurora: a new model and architecture for data stream management
This paper describes the basic processing model and architecture of Aurora, a new system to manage data streams for monitoring applications. Monitoring applications differ substant...
Daniel J. Abadi, Donald Carney, Ugur Çetintemel, ...
DSD
2008
IEEE
136views Hardware» more  DSD 2008»
15 years 10 months ago
Flexible Baseband Architectures for Future Wireless Systems
— The mobile communication systems today, have different radio spectrum, radio access technologies, and protocol stacks depending on the network being utilized. This gives rise t...
Najam-ul-Islam Muhammad, Rizwan Rasheed, Renaud Pa...
ICIP
1998
IEEE
16 years 5 months ago
Hardware Architecture for Optical Flow Estimation in Real Time
Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. In this work a specific a...
Aitzol Zuloaga, José Luis Martín, Jo...
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CODES
2005
IEEE
15 years 10 months ago
Energy conscious online architecture adaptation for varying latency constraints in sensor network applications
Sensor network applications face continuously changing environments, which impose varying processing loads on the sensor node. This paper presents an online control method which a...
Sankalp Kallakuri, Alex Doboli