6819 search results - page 213 / 1364 » Process Reuse Architecture |
158
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AHS
2006
IEEE
15 years 10 months ago
2006
IEEE
— This invited paper overviews the low level debug support hardware required for an on-chip predeployment debugging system for sensor networks. The solution provides significant...
110
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ICSM
2006
IEEE
15 years 10 months ago
2006
IEEE
— Software maintenance tools for program analysis and refactoring rely on a meta-model capturing the relevant properties of programs. However, what is considered relevant may cha...
111
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DAC
2006
ACM
15 years 10 months ago
2006
ACM
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric insert...
143
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DAC
2006
ACM
15 years 10 months ago
2006
ACM
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
116
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FPL
2004
Springer
15 years 9 months ago
2004
Springer
Abstract. Increasing logic resources coupled with a proliferation of integrated performance enhancing primitives in high-end FPGAs results in an increased design complexity which r...