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ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
15 years 11 months ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
ICIP
2004
IEEE
16 years 7 months ago
An implemented architecture of deblocking filter for H.264/AVC
H.264/AVC is a new international standard for the compression of natural video images, in which a deblocking filter has been adopted to remove blocking artifacts. In this paper, w...
Bin Sheng, Wen Gao, Di Wu
GCSE
2001
Springer
15 years 10 months ago
Scenario-Based Generation and Evaluation of Software Architectures
Architecture conception is a difficult and time consuming process, requiring advanced skills from the software architect. The tasks of an architect are alleviated if means can be p...
Hans de Bruijn, Johannes C. van Vliet
ACL
2001
15 years 6 months ago
From RAGS to RICHES: Exploiting the Potential of a Flexible Generation Architecture
The RAGS proposals for generic specification of NLG systems includes a detailed account of data representation, but only an outline view of processing aspects. In this paper we in...
Lynne J. Cahill, John Carroll, Roger Evans, Daniel...
VLSID
2004
IEEE
170views VLSI» more  VLSID 2004»
16 years 5 months ago
On-chip networks: A scalable, communication-centric embedded system design paradigm
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf