6819 search results - page 240 / 1364 » Process Reuse Architecture |
276
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DAC
2011
ACM
14 years 5 months ago
2011
ACM
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
124
Voted
DAC
2008
ACM
2008
ACM
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
16 years 6 months ago
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
153
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DAC
2003
ACM
2003
ACM
A complexity effective communication model for behavioral modeling of signal processing applications
16 years 6 months ago
In this paper, we argue that the address space of memory regions that participate in inter task communication is over-specified by the traditional communication models used in beh...
148
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DAC
2009
ACM
16 years 11 days ago
2009
ACM
It is unknown how to include stochastic process variation into fast-multipole-method (FMM) for a full chip capacitance extraction. This paper presents a parallel FMM extraction us...
124
Voted
DATE
2009
IEEE
16 years 9 days ago
2009
IEEE
this paper proposes a novel Process Variation Aware SRAM architecture designed to inherently support voltage scaling. The peripheral circuitry of the SRAM is modified to selectivel...