51 search results - page 4 / 11 » Process Variation Tolerant 3T1D-Based Cache Architectures |
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
- Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may e...
DATE
2008
IEEE
14 years 22 days ago
2008
IEEE
We present the implementation and analysis of a variation tolerant version of a switch-to-switch link in a NoC. The goal is to tolerate the effects of process variations on NoC ar...
MICRO
2009
IEEE
14 years 27 days ago
2009
IEEE
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
ISCA
2005
IEEE
13 years 12 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
HPCA
2009
IEEE
14 years 1 months ago
2009
IEEE
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...