51 search results - page 6 / 11 » Process Variation Tolerant 3T1D-Based Cache Architectures |
128
Voted
ISLPED
2007
ACM
15 years 5 months ago
2007
ACM
In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in th...
191
Voted
HPCA
2004
IEEE
16 years 4 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
183
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HPCA
2011
IEEE
14 years 7 months ago
2011
IEEE
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
113
Voted
ICCAD
2006
IEEE
16 years 17 days ago
2006
IEEE
We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the hi...
136
Voted
IPPS
2010
IEEE
15 years 1 months ago
2010
IEEE
Over the last 2-3 years, the importance of data-intensive computing has increasingly been recognized, closely coupled with the emergence and popularity of map-reduce for developin...