51 search results - page 8 / 11 » Process Variation Tolerant 3T1D-Based Cache Architectures |
110
Voted
DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
ICASSP
2011
IEEE
14 years 3 months ago
2011
IEEE
This paper presents an approach to designing narrowband digital filters that are realizable using optical allpass building blocks. We describe a top-down design method by explici...
HPCA
2002
IEEE
16 years 13 hour ago
2002
IEEE
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
ISCA
2010
IEEE
15 years 4 months ago
2010
IEEE
As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whe...
119
Voted
HPCA
2006
IEEE
16 years 14 hour ago
2006
IEEE
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...