2544 search results - page 118 / 509 » Process pipeline scheduling |
132
Voted
ASYNC
2003
IEEE
15 years 10 months ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
MICRO
2000
IEEE
15 years 9 months ago
2000
IEEE
Current superscalar microprocessors’ performance depends on its frequency and the number of useful instructions that can be processed per cycle (IPC). In this paper we propose a...
134
Voted
PODC
2010
ACM
15 years 9 months ago
2010
ACM
This paper deals with pipelined queries over services. The execution plan of such queries defines an order in which the services are called. We present the theoretical underpinni...
142
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APCCAS
2006
IEEE
15 years 8 months ago
2006
IEEE
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...
185
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COLING
2010
15 years 21 hour ago
2010
Semantic role labeling (SRL) and word sense disambiguation (WSD) are two fundamental tasks in natural language processing to find a sentence-level semantic representation. To date...