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ISCC
2003
IEEE
15 years 2 months ago
Pipelined Maximal Size Matching Scheduling Algorithms for CIOQ Switches.
In this paper, we propose new pipelined request-grant-accept (RGA) and request-grant (RG) maximal size matching (MSM) algorithms to achieve speedup in combined input and output qu...
Mei Yang, Si-Qing Zheng
DPD
1998
141views more  DPD 1998»
14 years 9 months ago
Dynamic Query Operator Scheduling for Wide-Area Remote Access
Distributed databases operating over wide-area networks such as the Internet, must deal with the unpredictable nature of the performance of communication. The response times of acc...
Laurent Amsaleg, Michael J. Franklin, Anthony Toma...
TVLSI
2008
115views more  TVLSI 2008»
14 years 9 months ago
Outer Loop Pipelining for Application Specific Datapaths in FPGAs
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
Kieron Turkington, Turkington A. Constantinides, K...
CGO
2004
IEEE
15 years 1 months ago
Single-Dimension Software Pipelining for Multi-Dimensional Loops
Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to outer loops. In this paper, we propose a threestep ap...
Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan...
ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
15 years 2 months ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak