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MICRO
2000
IEEE
95views Hardware» more  MICRO 2000»
15 years 1 months ago
Very low power pipelines using significance compression
Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This s...
Ramon Canal, Antonio González, James E. Smi...
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
15 years 3 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
CCE
2004
14 years 9 months ago
Optimal scheduling of multiproduct pipeline systems using a non-discrete MILP formulation
Multiproduct pipelines permit to transport large volumes of a wide range of refined petroleum products from major supply sources to distribution centers near market areas. Batches...
Diego C. Cafaro, Jaime Cerdá
SCOPES
2005
Springer
15 years 3 months ago
Generic Software Pipelining at the Assembly Level
Software used in embedded systems is subject to strict timing and space constraints. The growing software complexity creates an urgent need for fast program execution under the co...
Daniel Kästner, Markus Pister
ISSS
1997
IEEE
83views Hardware» more  ISSS 1997»
15 years 1 months ago
A Scheduling and Pipelining Algorithm for Hardware/Software Systems
Given a hardware/software partitioned specification and an allocation (number and type) of processors, we present an algorithm to (1) map each of the software behaviors (or tasks...
Smita Bakshi, Daniel Gajski