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DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 11 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
168
Voted
CP
1998
Springer
15 years 10 months ago
Modelling CSP Solution Algorithms with Petri Decision Nets
The constraint paradigm provides powerful concepts to represent and solve different kinds of planning problems, e. g. factory scheduling. Factory scheduling is a demanding optimiz...
Stephan Pontow
CN
2006
99views more  CN 2006»
15 years 6 months ago
High-performance switching based on buffered crossbar fabrics
As buffer-less crossbar scheduling algorithms reach their practical limitations due to higher port numbers and data rates, internally buffered crossbar (IBC) switches have gained ...
Lotfi Mhamdi, Mounir Hamdi, Christopher Kachris, S...
GRID
2006
Springer
15 years 6 months ago
Multi-Replication with Intelligent Staging in Data-Intensive Grid Applications
Existing data grid scheduling systems handle huge data I/O via replica location services coupled with simple staging, decoupled from scheduling of computing tasks. However, when th...
Yuya Machida, Shin'ichiro Takizawa, Hidemoto Nakad...
160
Voted
FASE
2010
Springer
16 years 29 days ago
Evaluating Ordering Heuristics for Dynamic Partial-Order Reduction Techniques
Actor programs consist of a number of concurrent objects called actors, which communicate by exchanging messages. Nondeterminism in actors results from the different possible orde...
Steven Lauterburg, Rajesh K. Karmani, Darko Marino...