2544 search results - page 18 / 509 » Process pipeline scheduling |
161
Voted
ICDE
2009
IEEE
15 years 11 months ago
2009
IEEE
94
Voted
CF
2008
ACM
14 years 11 months ago
2008
ACM
This paper contributes and evaluates a model and a methodology for implementing parallel wavefront algorithms on the Cell Broadband Engine. Wavefront algorithms are vital in sever...
FPL
2003
Springer
15 years 2 months ago
2003
Springer
We discuss high-performance programmable asynchronous pipeline arrays (PAPAs). These pipeline arrays are coarse-grain field programmable gate arrays (FPGAs) that realize high data...
107
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HPCA
1995
IEEE
15 years 1 months ago
1995
IEEE
The throughput of a multiple-pipelined processor suffers due to lack of sufficient instructions to make multiple pipelines busy and due to delays associated with pipeline depende...
ICCS
2004
Springer
15 years 3 months ago
2004
Springer
We show in this paper how to evaluate the performance of skeleton-based high level parallel programs. Since many applications follow some commonly used algorithmic skeletons, we id...