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BIOINFORMATICS
2011
14 years 1 months ago
A pipeline for RNA-seq data processing and quality assessment
Angela Goncalves, Andrew Tikhonov, Alvis Brazma, M...
JUCS
2007
124views more  JUCS 2007»
14 years 9 months ago
Pipeline-scheduling Simulator for Educational Purpose
: This paper presents a project that provides both, to professors and to students, a tool that is useful for studying, teaching and learning how pipelines work and how they can be ...
José M. Chaves-González, Miguel A. V...
MICRO
1992
IEEE
133views Hardware» more  MICRO 1992»
15 years 1 months ago
Code generation schema for modulo scheduled loops
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
B. Ramakrishna Rau, Michael S. Schlansker, Parthas...
VLSID
1993
IEEE
234views VLSI» more  VLSID 1993»
15 years 1 months ago
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs
High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both...
Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V....
ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
15 years 2 months ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...