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PACS
2004
Springer
115views Hardware» more  PACS 2004»
15 years 11 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
CC
2008
Springer
193views System Software» more  CC 2008»
15 years 8 months ago
Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model
The polyhedral model provides powerful abstractions to optimize loop nests with regular accesses. Affine transformations in this model capture a complex sequence of execution-reord...
Uday Bondhugula, Muthu Manikandan Baskaran, Sriram...
TPDS
2002
142views more  TPDS 2002»
15 years 5 months ago
MediaWorm: A QoS Capable Router Architecture for Clusters
With the increasing use of clusters in real-time applications, it has become essential to design high performance networks with Quality-of-ServiceQoS guarantees. In this paper, we...
Ki Hwan Yum, Eun Jung Kim, Chita R. Das, Aniruddha...
DAC
2006
ACM
16 years 7 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...
DAC
2005
ACM
16 years 7 months ago
System-level energy-efficient dynamic task scheduling
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...
Jianli Zhuo, Chaitali Chakrabarti