2544 search results - page 280 / 509 » Process pipeline scheduling |
165
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VLSID
2004
IEEE
16 years 6 months ago
2004
IEEE
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
154
Voted
FCCM
2009
IEEE
16 years 27 days ago
2009
IEEE
This paper presents an architecture for FPGA acceleration of quadrature methods used for pricing complex options, such as discrete barrier, Bermudan, and American options. The arc...
134
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IEEEPACT
2007
IEEE
16 years 13 days ago
2007
IEEE
The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. Howe...
147
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VR
2007
IEEE
16 years 12 days ago
2007
IEEE
Autostereoscopic displays enable unencumbered immersive virtual reality, but at a significant computational expense. This expense impacts the feasibility of autostereo displays in...
161
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CCECE
2006
IEEE
16 years 6 days ago
2006
IEEE
Single-sensor imaging pipelines comprised of various image compression and demosaicking solutions are presented. Since the end-user usually inspects captured images available in t...