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DAC
1992
ACM
15 years 1 months ago
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Ing-Jer Huang, Alvin M. Despain
IPPS
2000
IEEE
15 years 2 months ago
Design and Evaluation of I/O Strategies for Parallel Pipelined STAP Applications
This paper presents experimental results for a parallel pipeline STAP system with I/O task implementation using the parallel file systems on the Intel Paragon and the IBM SP. In ...
Wei-keng Liao, Alok N. Choudhary, Donald Weiner, P...
GIS
2008
ACM
15 years 10 months ago
Low-cost orthographic imagery
Commercial aerial imagery websites, such as Google Maps, MapQuest, Microsoft Virtual Earth, and Yahoo! Maps, provide high- seamless orthographic imagery for many populated areas, ...
Peter Pesti, Jeremy Elson, Jon Howell, Drew Steedl...
RTS
2006
129views more  RTS 2006»
14 years 9 months ago
Modeling out-of-order processors for WCET analysis
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...
Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
CONPAR
1994
15 years 1 months ago
A Framework for Resource-Constrained Rate-Optimal Software Pipelining
The rapid advances in high-performancecomputer architectureand compilationtechniques provide both challenges and opportunitiesto exploitthe rich solution space of software pipeline...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...